Stats

  • Locked Locked
  • Replies 0
  • Subscribers 164
  • Views 12362
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog Simulation in Board Flow for a FLAT schematic.

archive

Hi all,

I'm not sure if this is the right section for my post. If not, please advice me the proper one.

Our schematics are generated in ConceptHDL and are flat. My memory module contains a connector, few DRAMs and several passive devices. I have the correct behavioral models of my components. Is it possible to perform logic simulation of the whole schematic?

My flat schematic seems the only obstacle. Currently I can simulate similer components (Drams)  in my design but soon as I try to connect them with other components e.g. connector , the setup fails due to pinmap (e.g. pin A0 in dram is defined INPUT while in connector it is INOUT).
 
Has anyone sucessfully accomplished the verilog simulation flow in Board Design?

Please help!

Thanks,
Saad.


Originally posted in cdnusers.org by Saad
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.