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Etch Length vs Rdly actual length

Lexj

To preface, I'm not a layout engineer, and I have little experience with layout tools.  That said, I'm using the Allegro free viewer to look at a BRD file for a Xilinx eval board.  I get how relative prop delay constraints work, but I'm confused as to the results I see in the report file.  Can someone explain the difference between the "Total etch length" and the "actual" length shown in the (RDly) line?

Thanks.

Item 57 < NET >

Net Name: FMC_HPC0_LA10_N
Member of Diff Pair: FMC_HPC0_LA10
Member of Bus: FMC_HPC0_LA_BUS

Pin count: 2
Via count: 2

Total etch length: 9052.231129
Total manhattan length: 4784.469 MIL
Percent manhattan: 189.20%

Pin Type SigNoise Model Location
--- ---- -------------- --------
U1.W4 BI (2899.0450 -4363.4860)
J5.C15 BI (3685.0000 -8362.0000)

No connections remaining

Properties attached to net
ECL
NO_TEST
BUS_NAME = FMC_HPC0_LA_BUS
TS_ALLOWED = ANYWHERE
RATSNEST_SCHEDULE = MIN_TREE
DIFFP_PHASE_TOL = 5 mil

Electrical Constraints assigned to net FMC_HPC0_LA10_N
relative prop delay: global group MG_FMC_HPC0_LA_BUS from J5.C15 to U1.W4 delta=0.0000 MIL tol=50.0000 MIL
static diff pair phase tolerance: 5 mil
pin order type: minimum tree

Constraint information:
(RDly) J5.C15 to U1.W4 min= 9615.1448 MIL max= 9715.1448 MIL actual= 9616.0783 MIL
target= (FMC_HPC0_LA29_P) J5.G30 to U1.U9
(3685.0000,-8362.0000) pin J5.C15,BI,TOP/TOP
35.3553 MIL cline TOP
(3710.0000,-8337.0000) via TOP/BOTTOM
8989.42 MIL cline 05_SIG2
(2918.4592,-4382.9002) via TOP/BOTTOM
27.4558 MIL cline TOP
(2899.0450,-4363.4860) pin U1.W4,BI,TOP/TOP,pin+Zall=563.8472 MIL

(SPhase) J5.C15 to U1.W4 min= 9612.0697 MIL max= 9622.0697 MIL actual= 9616.0783 MIL
DPData: gap=var (--0.0001,+0.0000) tolerance= 5.0000; max uncoupled= -0.0001
(3685.0000,-8362.0000) pin J5.C15,BI,TOP/TOP
35.3553 MIL cline TOP
(3710.0000,-8337.0000) via TOP/BOTTOM
8989.42 MIL cline 05_SIG2
(2918.4592,-4382.9002) via TOP/BOTTOM
27.4558 MIL cline TOP
(2899.0450,-4363.4860) pin U1.W4,BI,TOP/TOP,pin+Zall=563.8472 MIL

  • mcatramb91

    Hello Lexj,

    I can see how this is confusing, let me start with the general differences.

    • "Total Etch Length" is length of all the connected etch for the net
    • "Actual" Length shown for Relative Delay is the length of etch between the pin pair that is being checked.

    In your example, it is only a two pin net so you would not expect the "Total Etch Length" being less than the "Actual" Length.  The design has Z-Axis delay enabled so the delay rules will include the length as the single travels down and up the Via/Pin holes to the reach its destination.

    • "Total Etch Length" = 9052.231129
    • Z-Axis delay "Zall" = 563.8472
      • Depth length of transition via at J5.C15 from TOP to 05_SIG2
      • Depth length of transition via at U1.W4 from 05_SIG2 to TOP
    • "Actual" Length shown for Relative Delay = 9616.0783

    One important note.  When Z-Axis delay is enabled it is very important to enter the correct "as fabricated" thickness' in the stack-up for the copper and dielectric layers.

    Hope this helps,
    Mike Catrambone

  • Lexj
    in reply to mcatramb91

    Thanks Mike, that's a good explanation for me.  I'm still uncertain about the "Zall" number in this example since it's 563 mils but the board is only 104 mils thick.  Maybe it's related to your important note, and the board thickness used in the analysis doesn't match the stackup I have.  Anyway, thanks for your help.  

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