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Why equal length?

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Hi all,
I selected the SDRAM interface signal quality parameter with Kai’s help. But a new problem comes out. I have to determine the trace length limitation of the interface through timing analysis. I wonder whether my understanding is right.
 
If the longest trace satisfies the timing analysis, there is no need to keep the data bus traces the same length. But it is said that the traces of the data bus should be equal length and the address bus also. Why? It confused me a long time.
 
Are there any other limitations, such as data bus vs. DQM…?
Would you please give me some suggestion?
 
Thanks in advance.


Originally posted in cdnusers.org by chenli
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    Originally posted in cdnusers.org by chenli
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