Constraints in the schematic (DEHDL)

Hi,

I'm using Cadence v17.2, Allegro Design Entry HDL for schematics and layout. At the moment, we have constraints at the schematic level (from an old design), and newer constraints in the layout.

Is there a way to remove all constraints and board information from the schematic, to ensure that only the layout has control over these? (The problem arises from the layout engineer adding constraints required, but then when the schematic is updated, the 'old' constraints in the schematic file are read through and changes the latest layout ones!

We've never had much success in the past ensuring the schematic and layout are in sync, and by default we only add constraints at the PCB level now to avoid this.... however, as this was an older design now in v17.2, I want to delete everything from the schematic side. Can it be done?!

Thanks