Need some advice on how to complete this one microprocessor connection.

Is there a clear path on an inner signal layer?   Can you "sneak" it in on a positive power layer?

Yeah, Component layers are usually blocked off with the "dogbone" fanout.

Should be no issue so you have something set wrong which Allegro/OrCAD is blocking trying to "help".  In the options tab turn the selection for "hug/hug preferred/slide/off" to OFF and make sure your find filter has pins, vias, clines clicked ON.  When you click on the starting pin (or via) it should allow you to route on the active layer unless you have the option of routing for that layer turned to OFF.

Once the route is completed, look at the DRCs to see what Allegro is complaining about and address the issue in CM or by sliding.

A picture of what's happening during routing would help immensely.

Hi, In this instance it looks to me that you have pins unconnected. If a rat is showing up it means something somewhere is not tied in. Here are a few steps that may help clear this up. You may already know some of these.

But before you try these, go to setup design parameters and see it "DiffPair driver pins is checked" If it is then un-check and see if the rat line disappears. It is possible it is not really a rat line so it's good to check first.

1 Go to the find filter and uncheck everything
2 Check the nets box so you can only select nets in the design
3 Hover over the pin that has a ratsnest showing up then right click and choose "Assign Color" Change the color of the net to something that will be easy to see on the design, Sometimes I use red.
4 Try locate where the net is going.
5 If you can see a route and it looks like it is routed in with a trace, Verify the padstacks that are used on the pcb footprints to make sure they do indeed have a pad on the layer that is routed in. If it is a ground or power net that are connected to a plane it is possible that the planes are not tied in.

In the visibility pane you can uncheck everything then check etch and cycle through the etch layers by enabling/disabling them to see where that route goes.

Hope this helps..

It doesn't allow me to make a connection anywhere along the pins because I assume it breaks some DRC.     I think the distance between pins is too small to allow a trace.

Hey excellon!, Thanks for replying!

Diffpair driver pin is unchecked.   Rat line still there.

Turned off everything in the find filter.   One thing to note here, is when I turn ratsnests off, the line DOES NOT disappear.

When I assigned color to net.


So i'm not finding anything out of the ordinary ( to my untrained eye), but I did find this in the log.  I'm not sure where this padstack is exactly, but I would be interested to know what it means.
"(SPMHA1-161): Cannot open the design because of database problems. Run the dbdoctor command on the design and try to open again.

(SPMHDB-95): Padstack 20RD10 not found. Purging it from DEFAULT constraint set will eliminate warning."

Could this be what's going on?