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Symmetrical stackup = asymmetrical impedance?

AndiLoop

Hello all together,

I'm trying to design my very first flex PCB with impedance 50 Ohm single ended and 100 Ohm differencial signals.

I have some problems to understand the calculation from Cadence in the stackup.

Its a three layer stackup and reference plane is GND in the middle.

From GND to TOP and BUTTON its symmetrical so I'm expecting equal impedance on both outer layers.
But Cadence seems to have another calculation.

What do I miss in this situation?

And as far as I understand Cadence only know single ended impedance.
So assuming a VERY large gap between two differential pairs each 50 Ohm impedance add together to 100 Ohm differencial.
So there is no way to get a correct impedance for parallel routed differencial pairs directly in Cadence from the contraint manager, right?

Thank you very much!

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  • jc teyssier

    Hello,

    a file named "interconn.iml" is created by allegro. It is a sort of cache of stackup to my understand.

    Sometimes, it is ot up to date (or corrupted?).

    I just have same behvoir: incorrect impedance calculation.

    In order to correct it, close allegro, remove interconn.iml and re-open allegro; the file will be re-created and now impedance calculation will be correct.

    Hope this help.

Reply
  • jc teyssier

    Hello,

    a file named "interconn.iml" is created by allegro. It is a sort of cache of stackup to my understand.

    Sometimes, it is ot up to date (or corrupted?).

    I just have same behvoir: incorrect impedance calculation.

    In order to correct it, close allegro, remove interconn.iml and re-open allegro; the file will be re-created and now impedance calculation will be correct.

    Hope this help.

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