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processor to L3_cache interface

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Hey all

In my design i am having processor to L3_cache interface in that  for Echoclock signal  going from L3_cache to processor when i did SI   i am getting Monotancity FAILs, i tryed to vary the length and resistor value even also i am not getting the result as PASS. my processor is at 2.5V and L3_Cache is at 1.5 v mode i selected  proper model for Simulation.
I am attaching the topology file any one can suggest me what i have to do next.


Originally posted in cdnusers.org by prashanthkumar.tm
topology.pdf
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    Thank you


    Originally posted in cdnusers.org by prashanthkumar.tm
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  • archive

    Thank you


    Originally posted in cdnusers.org by prashanthkumar.tm
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