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Allegro Design Entry HDL Hierarchy Design

mvs6013

I'm trying to use a hierarchy design in my schematic. I have 4 channels that will all have the same circuitry, so this will make it much easier. 

When I generate the block and add a schematic to it, how do I use local net names to go between the schematic pages within the block? When I use in/out ports, it thinks that these should be routed out to the block and do not just stay as local net names within this part of the hierarchy.

Another question is how to use local voltage rails inside of the hierarchy and how to pass in an outside voltage rail?

Is there a document with a guide on how to do this?

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  • I have a similar issue. I have a 20 page flat design but I want to use an overview block to navigate to sub pages. I cannot find any information in the top down or bottom up documents to enable me to do this. My other alternative is to attempt to make each sheet (20 in total) into a Hierarchy block (20 blocks with 20 separate sub folders) and this will be a long and involved process, on a time critical design.

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  • I have a similar issue. I have a 20 page flat design but I want to use an overview block to navigate to sub pages. I cannot find any information in the top down or bottom up documents to enable me to do this. My other alternative is to attempt to make each sheet (20 in total) into a Hierarchy block (20 blocks with 20 separate sub folders) and this will be a long and involved process, on a time critical design.

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