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  3. Extracting 'real' flight times from SigXP & PCB SI

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Extracting 'real' flight times from SigXP & PCB SI

archive
archive over 18 years ago

I need to be able to extract flight times from SigXP or PCB SI reports in order to feed them back into my STA tool.
The time that I need is the time from the driver output reaching Vmeas to the receiver input reaching its Vin threshold (Vinh or Vinl) - this prevents the double counting problems as detailed in the PCB SI User Guide Appendix E.
On first inspection it would appear that the SettleDelay measurement provides this functionality, but there is a problem with this.:
The SettleDelayRise is calculated as (Last time above Vihmin - driver RiseBufferDelay).  
But, the RiseBufferDelay value used is the buffer delay into a standard load (as defined in the IBIS model) and not the buffer delay with the simulated load applied.
If the standard load is different from the actual load (as will always be the case) the SettleDelay measurement will not be correct.
For example:
74LCX16245 buffer has a standard load defined as 75R and this leads to  BufferDelay(standardLoad) = 2.83ns

When I perform a simulation with a 22R output series term I get
BufferDelay(actualLoad) = 1.72ns (by examining waveform)
Last time above Vihmin = 2.73ns

The reported SettleDelay  = -0.1ns (calculated from 2.73 - 2.83)
Obviously a flight time of -0.1ns is not valid. The actual time that I want reported is 2.73-1.72=1.01ns.

Does this mean that there is no standard measurement that can be extracted to represent flight time?
Is the only around this to create some custom measurements?
or am I going about this the wrong way!


Originally posted in cdnusers.org by brynholmes
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  • archive
    archive over 18 years ago

    Bryn:

    The time to clock out numbers for the buffer are specified in terms of the standard load. When you simulate into a non-standard load, the flight time, when the standard buffer delay is subtracted, will be longer if you have a heavier load and less if you have a lighter load. This is why you can get a negative switch or settle delay from a lightly loaded case. This is the time you want to enter into your STA spreadsheet since it prevents double counting of the standard load buffer delay and takes into account the actual load.

    If you want to create a buffer delay for a non-standard load, just change the load parameters in the IBIS file to the ones you want but be careful about how you are using it. If you are only doing relative delay measurements, you can turn off the buffer delay by selecting "no buffer delay."

    Cheers,


    Originally posted in cdnusers.org by Kalevi2
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