Stats

  • Locked Locked
  • Replies 0
  • Subscribers 165
  • Views 12174
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to fix convergence problem in SigXplorer?

caddis

Hi, 

I am performing "tlsim" simulations on a net in SigXplorer that I have extracted from PCB Editor. Occasionally, I fail to run the simulation because I get a serious warning about a convergence problem.

The weird thing is, I have successfully simulated the same net with the same simulation parameters before. So I feel like there is no problem with my setup, these convergence warnings seem to pop up at random.

Has anyone else experienced the same thing? Any ideas on how to work around it?

Thanks.

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.