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RockeIO Syskit simulation using Sigxp

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We have downloaded the Virtex4_syskit for using Rocket IO buffer models. The Kit works with standalone Synopsys HSPICE simulator . To use these models in Cadence Allegro SI simulation we have encapsulated these models in Cadence native DML format. The vendor supplied encrypted HSPICE I/O models are encapsulated in a DML macromodel , as described in the document ‘ How to aSIhspice.pdf ‘ and’ Howto wrapHSPICE.pdf ‘ from Cadence support. We have also included the necessary Hspice options and parameters required for the simulation. We find that the netlist is being generated correctly. We need the clarifications for the following 1. The Hspice simulator (Synopsys) on reading the encrypted RocketIO models gives the following error while reading the included file for receiver model . **warning** unrecognizable command card. We have attached the TX and RX DML file for the reference. Please guide us for the same. 2. The example spice deck file in the sisKit has a PRBS generator included. We have included the PRBS input by a subcircuit call(This is in the stimulus directory of the Virtex4_syskit named vsource_no_jitter_2pt5_Gbps.inc) in the body of the macromodel. Parameters required for simulation are also included. The extracted topology needs a custom stimulus to be defined for the active driver , i.e. the buffer model for RocketIO Tx differential buffer. How are the two inputs , i.e. the PRBS input (subcircuit call ) and custom stimulus treated in this case? Is there any error in constructing our macromodels. 3. designname.tr0 have been generated from the HSPICE run by giving the option ‘csdf’ in hspiceoptions. Can these files be viewed in Avanwaves?


Originally posted in cdnusers.org by jaya
rocket_tx.zip
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    Hi Jaya,

    I'd like to suggest that you look at the Virtex II Pro Kit from Xilinx (Virtex-II Pro Signal Integrity Simulation Kit v3.7) combined together with the Xilinx RocketIO Design-in kit from Cadence (http://www.cadence.com/community/allegro/silicon_designin/kits.aspx?type=FPGA&sort=&abs=1&exclude=).

    The two kits combine together to present working examples of simulating RocketIO HSpice models in the Allegro PCB SI and SigXp environment.

    Best regards,

    brad


    Originally posted in cdnusers.org by bgriffin
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    Hi Brad,

    As per your suggestion I looked into the Virtex- II Pro kit from Xilinx.

    I could run the example simulations there.
    Also we assigned the Virtex-II pro RocketTx and RocketRx macromodels to our design , (which actually uses Virtex -4 device) . This also works fine . I guess that there is a problem in our macromodels(which use Virtex4 SPICE models) in  the way that the PWL stimulus is fed to the macromodel .

    Can I get some help regarding this?

    Regards.


    Originally posted in cdnusers.org by jaya
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    Hi Brad,

    As per your suggestion I looked into the Virtex- II Pro kit from Xilinx.

    I could run the example simulations there.
    Also we assigned the Virtex-II pro RocketTx and RocketRx macromodels to our design , (which actually uses Virtex -4 device) . This also works fine . I guess that there is a problem in our macromodels(which use Virtex4 SPICE models) in  the way that the PWL stimulus is fed to the macromodel .

    Can I get some help regarding this?

    Regards.

    -- jaya


    Originally posted in cdnusers.org by jaya
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    It appears I am running successfully the Virtex-5 FPGA RocketIO Transceiver Signal Integrity Simulation Kit (v5_rio_sis_kit_2_0) version 2.0 release date 5/14/2008. I have a SPICE license but not Avanwaves. I am using Hspui for Windows A-2008.3 Does anyone know if I can view the results in Allegro SI if I don't have an Avanwaves license? Also I have run the Virtex II Pro SI Simulation Kit 3.0 sis_kit_v2p_v3.7 and it runs good. But I now want to use it for the Virtex 5. How difficult is it to change it to run the Virtex 5?


    Originally posted in cdnusers.org by cswanson@integritysim.com
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    Two ideas: First, contact Xilinx. They need to know that you want to use their models in the Allegro PCB SI environment. That will enable more collaboration between Xilinx and Cadence. Second, contact your local Cadence field application engineer. He can get you started on the steps required for Allegro PCB SI to work with HSpice models so that you can use the HSpice simulation engine option.

    brad


    Originally posted in cdnusers.org by bgriffin
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