How to route 134-VFBGA 0.6mm 10x11.5mm LPDDR2 Package?

Specifically, Micron MT42L64M32D2HE-18 IT:D, but seems to apply to most any other LPDDR2 part.  They come in bigger, easier PoP packages, but we've been urged away from that package.

I am struggling at figuring out how to breakout this part.  My standard vias are 17C8D from L1-L8, but these are too large to fit between pads.  My microvias are 10C5D form L1-L2, but don't help me near enough as they only go down to 1 routing layer.  A second microvia from L2-L3 would be cool, but L3 is not a routing layer.  A buried via from L2-L7 with the same specs as my microvia might be helpful, but my CM's PCB vendor says the buried vias need to be the size of my standard via.  These won't fit in between the pads, as stated before, or the microvias on L2.  Trying to do this by routing on the top layer to vias outside the package isn't ideal for LPDDR2 impedances.  Maybe routing some of those out on L2 to standard vias might be doable, but it feels like it's getting messy, as well as that would make 3 vias per net and I've read it's better to be at 2 for LPDDR2 (I try to minimize the vias on nets like this anway).  Lastly, if I microvia L1-L2 the ground pins, they get to the L2 ground plane, which is pretty much my reference plane, but they don't stitch to other ground layers/pours unless I route them out too.

I hope I'm making sense here. Clearly this can be done, so I think I'm just missing some technique.

TL;DR, Does anyone have any tricks/tips/suggestions on breaking out a 0.65mm package for LPDDR2?

Thanks.