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DRC checks for covers

Lock2002

Most of our designs are RF and we require channelized metal cover for isolation. More than once we've had via shorting issues due to either overlooking it or last minute changes. I'd like to be able to setup constraints for a DXF layer that represents the cover to any copper that's hot (any net other than ground/return). Is this possible? I'm using Cadence 17.2 PCB Designer. No other add-ons
Thanks

  • RFinley

    From your DXF of the mating surface, make static shapes  on etch layers for the touchdown assigned to your shield/gnd net.  You can z-copy this to the mask layers.

    Cadence does not trim static shapes automatically, so you can trust it to be a solid netlist DRC item.  And you can zcopy them bigger or (probably not) smaller for tolerance

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