• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design
  3. overlapped Vias with the same net - How to create a rule...

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 167
  • Views 3758
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

overlapped Vias with the same net - How to create a rule to find the vias

Mikanu
Mikanu over 4 years ago

Hi to all,

I' m working on PCB that I have got from another collegue.

I have an little request: I have overlapped some vias with the same net.

What I can do is to create an proper rule in constraint in order to find this vias and delete one of them

Can someone help me?

mY orcad is 17.4 2019

.

  • Cancel
  • redwire
    redwire over 4 years ago

    There are rules to "find" the problem but not "delete" the problem.  Are you versed in scripting?  If so, you can run this SKILL routine to list, take the output to Excel, and generate a script to delete one or more of the multiple vias.  Sorry no further help than that but study this and it should help.

    /*
    This routine creates a report of all the vias in the design.
    Open a design with vias and at the Allegro command line type:
    load "myCompanyViaReport.il" <enter>
    myCompanyViaReport <enter>
    */
    axlCmdRegister( "myCompanyViaReport" `myCompanyViaReport)

    (defun myCompanyViaReport () ; Find all of the vias in the design
    allViasInDesign=list()
    originalVisible=axlVisibleGet()
    designName = axlCurrentDesign()
    axlVisibleDesign(t)
    axlShell("redisplay")
    axlSetFindFilter(?enabled '(noall vias) ?onButtons '(noall vias))
    allViasInDesign=axlGetSelSet(axlAddSelectAll())
    axlClearSelSet()
    ; Open a file to work on
    if(length(allViasInDesign)==0
    then
    axlUIConfirm("No vias in this design. Please try another design.")
    else
    writeOutFile = outfile("./myCompanyDesignViaReport.csv" "w")
    fprintf(writeOutFile strcat("Design Via Report for " designName "\n\n"))
    fprintf(writeOutFile "Via Location,Via Net Name,Padstack Name,Via Start
    Layer,Via End Layer\n")
    ; Output data for each via to the file
    foreach(via allViasInDesign
    viaLocation = sprintf(nil "%L:%L" car(via->xy) cadr(via->xy))
    fprintf(writeOutFile strcat(viaLocation ","))
    fprintf(writeOutFile strcat(via->net->name ","))
    fprintf(writeOutFile strcat(via->name ","))
    fprintf(writeOutFile strcat(car(via->startEnd) ","))
    fprintf(writeOutFile strcat(cadr(via->startEnd) "\n"))
    );end foreach via allViasInDesign
    ; Close the file and wrap up
    fprintf(writeOutFile "END OF FILE")
    close(writeOutFile)
    axlVisibleSet(originalVisible)
    axlShell("redisplay")
    axlUIConfirm( "Report has been generated in your working directory." )
    ; This next line launches Excel and displays the report
    axlHttp("myCompanyDesignViaReport.csv")
    );end if length(allViasInDesign)==0
    );end defun myCompanyViaReport

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • steve
    steve over 4 years ago

    Because these aren't coincident look at Enabling the Same net spacing rules for Via - Via. These need to be enabled using Setup - Constraint Modes - Same Net Spacing and also in Constraint Manager - Same Net Spacing Constraint Set turn on the Enable DRC by Layer. This will show a DRC flag for everything that violates the rules. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information