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keepout question

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I want to create a bottom keepout area:
-no bottom component placement
- no vias
-no bottom etch

I've created a bottom keepout area:
when I place a through hole e-cap on the top I don't get any DRC error.

How can I get a DRC error when a through hole component is placed on the top?

Thanks,


Originally posted in cdnusers.org by mihaii
Parents

  • Defining PLACE_BOUND_TOP shapes in your package symbols is a standard part of good library development. Every through-hole part is also present on the second side of the PCB (where the leads protrude or are clinched perhaps). Therefore it is good library development practice to define PLACE_BOUND_BOTTOM shapes describing these areas where the leads are present. Incorporating this as part of your lib development process requires very little extra time and will address your immediate problem.


    Originally posted in cdnusers.org by AshCan
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  • Defining PLACE_BOUND_TOP shapes in your package symbols is a standard part of good library development. Every through-hole part is also present on the second side of the PCB (where the leads protrude or are clinched perhaps). Therefore it is good library development practice to define PLACE_BOUND_BOTTOM shapes describing these areas where the leads are present. Incorporating this as part of your lib development process requires very little extra time and will address your immediate problem.


    Originally posted in cdnusers.org by AshCan
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