Sigrity System Explorer/Speed2000 sim: Simulation with long duration ends with 'Simulation Aborted'

I admit that I'm a rookie concerning using the Sigrity suite, but I have come across a problem that I can't solve.

I doing a fairly simple transient simulation of a 40 MHz bus between a Xilinx SoC and two parallel NAND flash chips.

The simulation setup was originally done and executed by our local Cadence rep as a paid service.

The PCB layout has now been revised, and I need to redo the simulations myself.

No problem for me to change the old revision layout with the new revision and do the setup and extraction.

Although I'm using quite a powerful PC for the simulation, it takes 24+ hours to complete, when using the 'Auto' setting for 'Time Step' and 'Time Stop'.

In this case 'Time Step' is 500 ps and 'Time Stop' is 501 ns.

There's no problem starting the simulation from System Explorer, which spawns the Speed2000 simulator, that starts to count down the time while i see a heavy load on the CPU cores. All is good.

After 24+ hours the time countdown finishes, Speed2000 simulator closes as normal, and System Explorer takes over - but the result is just a popup saying 'The simulation was aborted' !

If I manually change 'Time Stop' to 200 ns, the duration of the simulation is significantly shorter (of course) - typically below 10 hours - and everything is fine. I get the simulation results in System Explorer and can generate a report and so on.

Is there a kind of timeout in System Explorer which assumes an error has occurred, if simulation isn't completed after a certain amount of time?