Hierarchical Net Naming

Hello,

I was wondering if someone could give me some advice on how to set up my Cadence DE HDL (17.2) hierarchical design. To start with a test schematic, I set up the following:

1. top level design is called "Top"

2. Created a sub-block called "PIN_CNTL". The block consists of a resistor with an input IN1 and an output OUT2 and another resistor with IN2 and OUT2.

3. Copied PIN_CNTL three additional times, so now I have a total of four instantiations.

4. Did a "Save Hierarchy" and "Export Physical" -- no errors

When I "descend" into each block, the net naming isn't what I'd expect. In the first block, it appends nothing to the net -- the nets are IN1, IN2, OUT1, OUT2. But when I descend into the 2nd block, the nets are "IN1_1", "IN2_1", "OUT1_1", and "OUT2_1". To me, this is confusing. Since this is the 2nd block, I'd like the appendices to be "_2". In summary --

What Cadence DE HDL named for nets:

1. Block 1: IN1, IN2, OUT1, OUT2

2. Block 2: IN1_1, IN2_1, OUT1_1, OUT2_1

3. Etc for Blocks 3 and 4.

What I _WANT_ (and is less confusing) -

1. Block 1: IN1_1, IN2_1, OUT1_1, OUT2_1

2. Block 2: IN1_2, IN2_2, OUT1_2, OUT2_2

3. Etc for blocks 3 and 4

Any idea how to force DE HDL to do this? Thank you!