Uprevising an old design with non synchronized design rules and no access to old versions of Cadence.

Hi All,

I have a collection of designs that use old versions of Cadence (<16.5 but >14.2) that i am unable to uprevise the schematic.  i currently use 17.2.

when I uprevise the schematic the process starts, I see two blobs text flash by the Details (presumably one for each page processed) window and it silently crashes on the third when calling van.exe.  The last blob of text is as follows and is truncated:

Spawning... csnetlister.exe -proj "S:\aaa\bbb\ftab_pca.cpm"  -renetlist
csnetlister 17.2-2016 S069 (3869965) 6/23/2020

Loading consmgr.cxt
Loading acns_formula.cxt
Loading design telephone
Loading connectivity of page 1
Found Bundled constraints in the design. Synchronizing constraints in schematic to constraint manager.Executing netassembler with preconfig mode
Executing Netlister for Design Language : Verilog, in mode : preconfig.
Reading Configuration: ftab_pca_lib ftab_pca cfg_package

van.exe  -nolinks -sironly -cdslib cds.lib "S:\aaa\bbb\worklib\power\sch_1\verilog.v" -lib "ftab_pca_lib" -view sch_1 -instanceview sch_1 -instanceview entity -define VAN -globals "ftab_pca_l

My feeling is that this is due to non-Synchronized Design rules between the Schematic and PCB, which are normally resolved by using Tools -> Constraints -> Synchronize inside the old version of Cadence.

The problem is that i no longer have access to any old versions of Allegro.  I'm not even sure what Cadence version the design was created in (not sure where to look for that information).

How can i successfully update the schematics to the current version of Allegro?  If it means throwing away all Constraints Manager information in the Schematic or the Design Environment, i'm happy with that and call it a win.

Robert.