IPCD356 Netlist problems

Hi
How did you create the buried resistors? Did you create a seperate layer and build the resistors out of Lines?
If you did then included the lines in your artwork you would receive shorts from the IPC356 Netlist. Since each
end of the buried resistor is on a different net when the resistor is added to the artwork it creates a short. Buried
resistors create challenges for Allegro. It and IPC think of resistors as components added after the board is built.
If you are on current maintance you can get the ODB++ from Valor for free and it includes the Valor viewer. It is
very dangerous and potentionaly expensive to send out gerber data without post process checking. The cost of
one set of bad boards is more expensive than one seat of a gerber tool like CAM350.

Hope I helped
Bill

Bill,

    I couldn't agree with you more. I have preached those same words to my management but they are so tigh that when you hold them upside down their change doesn't fall out of their pockets. Apperently they have more faith in me than they have in tools like that and don't see the need as I have not yet given them a bad board to work with. But I feel I am living on borrowed time here with the technologies I am getting into and given the limits of Allegro DRC system, which really in all is the best I have worked with as far as PCB design goes.

I created the buried resistors as component which came from the ORCAD schematic the pins are modeled as padstacks on the specific layers they are designed on. There is a second artwork layer is generated for 2nd etch process for the resistive material that is model as a shape on the package geometry layer. I can't see any reference to that in the IPC netlist.
 
Anyway the problem turns out to be a netlist interpreatation problem on Valors part but maybe someone from Cadence wants to look into this also since they are connection partners. This is directly from TYCO

Silverstorm P/N 310034-000 Rev 0

Tyco/Dallas T-22633

Investigate/Document CAD netlist issue

After analyzing the data and the CAD netlist files, I have found that all the issues were caused by translation errors.

Most of these have to do with the format of the buried resistor networks and blind vias in the netlist text file.

I've detailed the issues below for customer information, but I'm approving the CAD netlist as verified to Gerber data.

--

Part of the resistor network contains the pad the resistor is tied to:

307MN_DQ31 R543 -2 P X+017495Y+033160X0000Y0000R270

S0L04L04

Our input is interpreting this as access side bottom, and creating issues when this runs into features on the bottom side. Due to the method of analysis in the Valor software this generates both shorted and broken networks.

Removing these lines from our file eliminates both errors.

Thanks Bill!

Can you raise a Service Request with Cadence? This way Cadence can look into the problem officially and pass it over to Valorif need be. Cadence will need a copy of the brd that you have, maybe also a IPC netlist pointing out the problem

Andy