Stats

  • Locked Locked
  • Replies 7
  • Subscribers 164
  • Views 19621
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Orcad to PCB Editor error during Create Netlist

archive

I obtain the following session log error when i tried to create netlist from Orcad Capture to be used by PCB Editor for layout. Kindly help. It seem to be due to naming conflict of component.

Is there a way to prevent the default naming component of Orcad to cascade during netlist creation?

many thanks

********************************************************************************
*
* Netlisting the design
*
********************************************************************************
Design Name:
Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\attocycler.dsn
Netlist Directory:
Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro
Configuration File:
C:\OrCAD\OrCAD_15.7\tools\capture\allegro.cfg

Spawning... "C:\OrCAD\OrCAD_15.7\tools\capture\pstswp.exe" -pst -d "Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\attocycler.dsn" -n "Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro" -c "C:\OrCAD\OrCAD_15.7\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
Scanning netlist files ...
Loading... Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro/pstchip.dat
Loading... Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro/pstchip.dat
Loading... Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro/pstxprt.dat
Loading... Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro/pstxnet.dat
packaging the design view...

Exiting... "C:\OrCAD\OrCAD_15.7\tools\capture\pstswp.exe" -pst -d "Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\attocycler.dsn" -n "Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro" -c "C:\OrCAD\OrCAD_15.7\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"


*** Done ***

********************************************************************************
*
* Updating Allegro PCB Editor Board
*
********************************************************************************
Netlist Directory:
Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro
Input Allegro Board:
Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd
Output Allegro Board:
Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd

Spawning... netrev.exe -5     -y 1 -n   -i "Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro" "Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd" "Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd"
Reading File : Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstchip.dat
(00:00:00.01)
Reading File : Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstxprt.dat
(00:00:00.00)
Reading File : Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstxnet.dat
(00:00:00.01)
Starting to process component instances

netrev run on Nov 16 11:20:54 2006
   DESIGN NAME : 'ATTOCYCLER'
   PACKAGING ON May 28 2006 22:05:31


  8 errors detected
 No oversight detected
 No warning detected

cpu time      0:00:18
elapsed time  0:00:00


Exiting... netrev.exe -5     -y 1 -n   -i "Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro" "Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd" "Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd"
Cadence Design Systems, Inc. netrev 15.7 Thu Nov 16 11:20:54 2006
(C) Copyright 2002 Cadence Design Systems, Inc.

------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR FALSE;
SCHEMATIC_DIRECTORY 'Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro';
BOARD_DIRECTORY 'Z:/Attogenix/Projects/Attocycler v2.0/Hardware/PCB/Cadence/Orcad/allegro';
OLD_BOARD_NAME 'Z:/Attogenix/Projects/Attocycler v2.0/Hardware/PCB/Cadence/Orcad/allegro/attocycler.brd';
NEW_BOARD_NAME 'Z:/Attogenix/Projects/Attocycler v2.0/Hardware/PCB/Cadence/Orcad/allegro/attocycler.brd';

CmdLine: netrev.exe -5 -y 1 -n -i Z:\ATTOGENIX\PROJECTS\ATTOCYCLER V2.0\HARDWARE\PCB\CADENCE\ORCAD\allegro Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd

------ Preparing to read pst files ------

Starting to read Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstchip.dat
   Finished reading Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstchip.dat (00:00:00.01)
Starting to read Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstxprt.dat
   Finished reading Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstxprt.dat (00:00:00.00)
Starting to read Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstxnet.dat
   Finished reading Z:/ATTOGENIX/PROJECTS/ATTOCYCLER V2.0/HARDWARE/PCB/CADENCE/ORCAD/allegro/pstxnet.dat (00:00:00.01)

------ Oversights/Warnings/Errors ------


#1   ERROR(302) Device library error detected.

Problems with device 'R_AX/RC05_15K'. JEDEC_TYPE property 'AX/RC05' is illegal: 'Package name has invalid characters or is too long.'.

Device 'R_AX/RC05_15K' has library errors. Unable to transfer to Allegro.

#2   ERROR(302) Device library error detected.

Problems with device 'R_AX/RC05_45K'. JEDEC_TYPE property 'AX/RC05' is illegal: 'Package name has invalid characters or is too long.'.

Device 'R_AX/RC05_45K' has library errors. Unable to transfer to Allegro.

#3   ERROR(302) Device library error detected.

Problems with device 'R_AX/RC05_22K'. JEDEC_TYPE property 'AX/RC05' is illegal: 'Package name has invalid characters or is too long.'.

Device 'R_AX/RC05_22K' has library errors. Unable to transfer to Allegro.

#4   ERROR(302) Device library error detected.

Problems with device 'R_AX/RC05_10K'. JEDEC_TYPE property 'AX/RC05' is illegal: 'Package name has invalid characters or is too long.'.

Device 'R_AX/RC05_10K' has library errors. Unable to transfer to Allegro.

#5   ERROR(302) Device library error detected.

Problems with device 'C_RAD/CK05_470N'. JEDEC_TYPE property 'RAD/CK05' is illegal: 'Package name has invalid characters or is too long.'.

Device 'C_RAD/CK05_470N' has library errors. Unable to transfer to Allegro.

#6   ERROR(302) Device library error detected.

Problems with device 'C_RAD/CK05_100N'. JEDEC_TYPE property 'RAD/CK05' is illegal: 'Package name has invalid characters or is too long.'.

Device 'C_RAD/CK05_100N' has library errors. Unable to transfer to Allegro.

#7   ERROR(302) Device library error detected.

Problems with device 'C_RAD/CK05_150N'. JEDEC_TYPE property 'RAD/CK05' is illegal: 'Package name has invalid characters or is too long.'.

Device 'C_RAD/CK05_150N' has library errors. Unable to transfer to Allegro.

------ Summary Statistics ------


#8   ERROR(102) Run stopped because errors were detected

netrev run on Nov 16 11:20:54 2006
   DESIGN NAME : 'ATTOCYCLER'
   PACKAGING ON May 28 2006 22:05:31

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

  8 errors detected
 No oversight detected
 No warning detected

cpu time      0:@Ú
00:18
elapsed time  0:00:00



*** Done ***

********************************************************************************
*
* Spawing Allegro PCB Editor
*
********************************************************************************
Spawing "C:\OrCAD\OrCAD_15.7\tools\pcb\bin\allegro.exe" -mpssession Administrator "Z:\Attogenix\Projects\Attocycler v2.0\Hardware\PCB\Cadence\Orcad\allegro\attocycler.brd"


*** Done ***


Originally posted in cdnusers.org by garylim
  • archive

    Gary,

    I am not sure if the the character '/' is giving you error. May be you can replace the value in schematic with underscore '_' and give a try.

    Try setting the system environmental variable ALLEGRO_LONG_PACKAGE and value as TRUE, this will allow to read in the netlist with long package names into allegro.

    Just a quick guess :-)

    Good Luck!!
    Raj.


    Originally posted in cdnusers.org by rajpcb
  • archive

    hi raj,

    Thanks for the fast response. Yes, we also suspect that was the issue. But it will be a integration nightmare to manual convert every component naming to fit Allegro requirement. Shouldn't cadence has design built in to rectify such integration problem?

    thanks for the ALLEGRO_LONG_PACKAGE tips.

    cheers
    gary


    Originally posted in cdnusers.org by garylim
  • archive

    garylim,

    i am so sorry to tell you that, maybe you have to modify the "pcb footprint" property of every component that caused error,

    some concept:

    property transition : Orcad Pcb footprint -> Allegro JEDEC

    there are no charactor available in "jedec" but english char like "a, b x..", numeric char like " 2 , 5 " and the underlin"_";

    and what's more, the design path of brds,symbles and pads do not permmit "space char" insede:)

    hope this helps


    Originally posted in cdnusers.org by tfsummer
  • archive

    and a number , 18 , is the longest char length of legal symbole and pad name:)


    Originally posted in cdnusers.org by tfsummer
  • archive

    I'm having a similair issue at the moment, I tried the underscore but it did not seem to work. I did this on a single part, I will try agian and see if this works. Its going to be a nightmare for me as well if I have to go and fix all the parts.


    Originally posted in cdnusers.org by Gun_metal
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.