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OrCad Layout to Allegro - Via Padstack Problem

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Attempting my first Layout to Allegro translation, and am getting an error :

ERROR (Layout To PCBEditor), Padstack 'V_TP_SM' is malformed on layer 1

The Layout padstack is a Via being used as a Testpoint on the Bottom surface only, so it is defined as having features on Layout Bottom and Bottom Soldermask only, all other layers are undefined.

Anyone run into a similar problem? The error logs that are created include only the information I've listed above.

Thanks,
Dave


Originally posted in cdnusers.org by dschaefer

  • I hink the via needs some sort of copper feature (pad) on the top layer. Allegro normally insists on having a coonect point at either end of a hole. If you don;t want it on your manufactured board make the feature smaller than the drilled hole.


    Originally posted in cdnusers.org by emldebh

  • Turns out I need an ISR to perform the translation.

    The design now translates, but I believe you are correct about the required features as I see other issues post-translation.

    Thanks!

    Dave


    Originally posted in cdnusers.org by dschaefer

  • Have translated a few Orcad designs and have noticed a few things that do not come through correctly. Here is a partial list.

    1. Planes do not come in.
    2. No anti-pad / thermal sizes in the padstacks.
    3. SMD pads defined from the bottom whilst the package geometry is defined from the top.
    4. Silkscreens and other aesthetics not read in.
    5. Many duplicate padstacks created of the same drill and pad features.
    6. Layer count incorrect.
    7. Extra holes, such as fixings, mechanicals missing.
    8. Basic constraints do not come through correctly.
    9. Some components do not get placed due to 'out of extents'. This is caused by the reference designators being offset.
    10. Board outline and internal board cut-outs missing.

    KP


    Originally posted in cdnusers.org by kp
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