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layout purposal

Please if you mention if you have any other suggestion or any amendment required.

Most effective and easy way to reduce X-talk is maximize the dielectric thickness between Dual-strip line layers. Recommendation is 3W minimum (where W=trace width). But larger the thickness the better. Second effective method is to reduce the length that two traces run parallel to each other (either on same layer or adjacent layers) as much as possible. Third step is to off-set (stagger) the traces in x/y co-ordinates so that actual distance b/w the traces is increased. This is less effective but still useful & required if you have less then 4W dielectric thickness. These parallelism constraints (as shown in your pictures) can be placed in the CM. In routing, only way to effectively deal with parallelism is to use horizontal traces on one layer and vertical traces on the other layer.
It’s easier for routing & manufacturing, if the Diff pair’s center to center distance to remains the same on all layers. Only the trace width is changed for different layers. This is a recommendation only. If we cannot get the required impedance values in this way, then changing the center to center distance for Diff pair’s is allowed. This is because the impedance is the requirement which needs to be met.
Yes, you can ask CAM department for general guidelines for class II requirements for different board thicknesses. But Routing Placement Section (RPS) decides which VIA sizes are required on the board and then have CAM dept. bless these from manufacturing point of view.
Keep 22 mils in z-axis clearance requirement for -48V nets for FR4 material. We used 15-18mils in that particular board after consultation with customer. Production board designs are strict about these requirements. While customer who are doing first prototype board might relax this requirement to 15-18 mils. Also this requirement is for Telecommunication boards/equipment only.
For Test-pads for ICT, recommended size is 35 mils. We should use this pad size if possible. But the ICT technology has improved over last few years, so after consultation with customer & his approval, we can use 30 mils pad or even 28 mils pad sizes for ICT.

1- To minimize the crosstalk at early stages especially in dual strip line stackup, we need to put enough dielectric thickness between the adjacent layers at stackup building level.

2- During stackup building process, CAM department gays should also need to follow such practice that they keep constant center to center distance in differential pair cases instead of varying only line width or air gap.

3- When we request to CAM department, also provide minimum PTH drill information in order to combat with aspect ratio issues.

4- The nominal breakdown voltages of FR4 dielectric is 65KV/sq inch, and in case of 48 volt power supply normally we consider 1.5KV/sq inch means we need round about 22 mil thickness to avoid from any breakdown but after consulting with you, suggest that 15 to 18 mil thickness in Z-axis is enough. So, please also consider it when we layout a board with -48Volt power supply.

5- With the passage of time electronic circuits are going to getting a miniature form (like a pressure cooker situation). So, we also need to redefine our standards. For example in test prep case usually we used a pad with solder mask opening 35 mil which is I think is very high value in most of the board file we doing now if we looking for near 100% test prep. In this situation we can adopt Foundry standards which have 28 to 32 mil opening.

Originally posted in cdnusers.org by imaqsood

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