• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design
  3. who does SI/PI simulations? the hw engineer or the layout...

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 164
  • Views 337
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

who does SI/PI simulations? the hw engineer or the layout designer?

admin
admin over 17 years ago

hi.

who does SI/PI simulations: hw engineer or layout designer?  if there is no SI engineer.
do all companies use the allegro simulation capabilities? (at least reflection analysis)

and anyway, how much control does the hardware engineer have over the layout:
can he say to the layout engineer this?-"put these 10 capacitors here and not there" or "put the termination here" or "make this splitplane wider"...

who specifies the layer stackup, materials, trace widths, footprint assigments, bus-layer assigments...

  • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information