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Embedded component question

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I have generated symbols for embedded resistors. I did not include a place_bound_top feature in the symbol, however when I place the component inside a board file a place_bound_top shape is being added. This behavior generates a number of unexpected package to package DRC errors. Is there anything that I can do to prevent this shape from being added?

Thanks,
Dan


Originally posted in cdnusers.org by do_eit

  • I should add that I am using Allegro PCB Editor 15.7.

    Thanks,
    Dan


    Originally posted in cdnusers.org by do_eit

  • Welcome to the world of unsupported embedded passives in Cadence. Here are the things you need to do.

    1) Complete your top care about survey and ram this home to Cadence that this is functionality completely missing in the tool set.
    2) Package boundaries come in by default in the tool you can either delete them or waive the DRC's to get rid of the DRC's You will also need to get rid of the Assembly reference designators that clutter up your assy drawing and really aren't there for the assembler to place. I myself like having the text some where so aI change the subclass to DISPLAY_TOP


    Originally posted in cdnusers.org by cmusetti@qlogic.com

  • Thanks for the input. I will follow up with Cadence.

    Dan


    Originally posted in cdnusers.org by do_eit
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