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High speed DDR multi-tiered T routing

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Hey all,

I'm trying to setup some matched length T routing for some high speed DDR memory. I have scheduled the nets properly with virtual pins and setup pin pairs in constraint manager under Relative Propagation Delay but I don't understand how to specify a length range for the individual pin pairs of the T route. Should this be setup somewhere besides Relative Prop Delay?

Image 1: multi-tiered T routing of DDR address buss. All segments A must match length. All segments B & C must match length. All segments D, E, F and G must match length. Data buss length must match address segment length to each DDR.

I'm running 15.5.1 with the performance option.

Any help would be appreciated....need to get moving on this board!!!!!


Originally posted in cdnusers.org by padmaster
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    Hi,
    Relative propagation delay is the corect place for this constraint to live.

    There are acoupel of ways of getting the constraint into the field. The easiest to visualise is through sigexplorer.

    Open constraint manager, find a representitve net, right click it and open sig xp for that net.

    It's probably worth spending a few minutes at this point cleaning up the canvas, so that the tlines and receivers are layed out as per your diagram above.

    Now use the menu and open "constraints" Move to the relative propagation delay.

    Here you must create a pin pair and matched group name for each of the lengths that you wish to constrain.

    I looks like you are laying out data, so may I suggest:

    ("MGx" = matched group name)

    "MG1" pin pair defining D, scope local.
    "MG1" pin pair defining E, scope local.
    "MG1" pin pair defining F, scope local.
    "MG1" pin pair defining G, scope local.

    These will match D, E, F & G within each net.

    Then:
    "MG2" pin pair defining A+B+D, scope global (or bus).
    Which will match the length of D + E within this net, either to all nets upon which you apply this ECSet (global) or to all nets within the current bus (bus scope.) This is the matched group that is used to tie the 8 data bits together with the strobe in a DDR bus.

    Once the constraints are all set up, save the topology from sigxp and import it into constraint manager as an ECSet. Then apply the EC Set to your databus.

    If you don't have Sigxp, you can do the same thing from constraint manager, but it's a little less visual. open a generic data bus net, and right click then create > pin pair to make the required pin pairs. Next fill in the constraints and scopes in the relative propagation box. Finally you create an ECSet from the gerneic net and apply as before.


    Can I point you at:
    http://www.cdnusers.org/community/allegro/Resources/kits_designin/memory/stp_cdnliveemea07_ddrconstraints_veal.pdf
    It's a presentation I wrote for CdnLive last year on DDR constraints, it might be useful to you.

    Hope that helps.






    Originally posted in cdnusers.org by vealmic@uk.ibm.com
Reply
  • archive

    Hi,
    Relative propagation delay is the corect place for this constraint to live.

    There are acoupel of ways of getting the constraint into the field. The easiest to visualise is through sigexplorer.

    Open constraint manager, find a representitve net, right click it and open sig xp for that net.

    It's probably worth spending a few minutes at this point cleaning up the canvas, so that the tlines and receivers are layed out as per your diagram above.

    Now use the menu and open "constraints" Move to the relative propagation delay.

    Here you must create a pin pair and matched group name for each of the lengths that you wish to constrain.

    I looks like you are laying out data, so may I suggest:

    ("MGx" = matched group name)

    "MG1" pin pair defining D, scope local.
    "MG1" pin pair defining E, scope local.
    "MG1" pin pair defining F, scope local.
    "MG1" pin pair defining G, scope local.

    These will match D, E, F & G within each net.

    Then:
    "MG2" pin pair defining A+B+D, scope global (or bus).
    Which will match the length of D + E within this net, either to all nets upon which you apply this ECSet (global) or to all nets within the current bus (bus scope.) This is the matched group that is used to tie the 8 data bits together with the strobe in a DDR bus.

    Once the constraints are all set up, save the topology from sigxp and import it into constraint manager as an ECSet. Then apply the EC Set to your databus.

    If you don't have Sigxp, you can do the same thing from constraint manager, but it's a little less visual. open a generic data bus net, and right click then create > pin pair to make the required pin pairs. Next fill in the constraints and scopes in the relative propagation box. Finally you create an ECSet from the gerneic net and apply as before.


    Can I point you at:
    http://www.cdnusers.org/community/allegro/Resources/kits_designin/memory/stp_cdnliveemea07_ddrconstraints_veal.pdf
    It's a presentation I wrote for CdnLive last year on DDR constraints, it might be useful to you.

    Hope that helps.






    Originally posted in cdnusers.org by vealmic@uk.ibm.com
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