Stats

  • Locked Locked
  • Replies 4
  • Subscribers 164
  • Views 14504
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

High speed DDR multi-tiered T routing

archive

Hey all,

I'm trying to setup some matched length T routing for some high speed DDR memory. I have scheduled the nets properly with virtual pins and setup pin pairs in constraint manager under Relative Propagation Delay but I don't understand how to specify a length range for the individual pin pairs of the T route. Should this be setup somewhere besides Relative Prop Delay?

Image 1: multi-tiered T routing of DDR address buss. All segments A must match length. All segments B & C must match length. All segments D, E, F and G must match length. Data buss length must match address segment length to each DDR.

I'm running 15.5.1 with the performance option.

Any help would be appreciated....need to get moving on this board!!!!!


Originally posted in cdnusers.org by padmaster
Parents
  • archive

    DQS actually starts life as a single ended signal. During bringup of the DDR interface the controller turns on differential DQS in the DRAM.

    DQS needs to be the target of thematched group for each data byte, regardless of whether it's a single ended or differential signal.

    It is not necessary to route the ADDR bus the same length to every chip. Doing so will quickly get your design all tangled up. Check the DRAM spec for clock to Address tolerance and then clock to data. You should find clock to addr is reasonably tight, but clock to data (strobe) is loose.

    So, make sure clock and ADDR arrive simultaneously at each DRAM. Don't worry about any skew between DRAM devices. Each DRAM has no knowledge of the 8 other DRAMS in the rank, so why does the address have to arrive at all drams simultaneously?

    Make sure each data byte is closely matched to it's strobe.

    Finally, make sure that the strobes are loosely aligned to the clock.

    If your customer is asking you to match Address to data, address (DRAM1) to address (DRAM 2) then I'm not sure they understand DDR.


    Originally posted in cdnusers.org by vealmic@uk.ibm.com
Reply
  • archive

    DQS actually starts life as a single ended signal. During bringup of the DDR interface the controller turns on differential DQS in the DRAM.

    DQS needs to be the target of thematched group for each data byte, regardless of whether it's a single ended or differential signal.

    It is not necessary to route the ADDR bus the same length to every chip. Doing so will quickly get your design all tangled up. Check the DRAM spec for clock to Address tolerance and then clock to data. You should find clock to addr is reasonably tight, but clock to data (strobe) is loose.

    So, make sure clock and ADDR arrive simultaneously at each DRAM. Don't worry about any skew between DRAM devices. Each DRAM has no knowledge of the 8 other DRAMS in the rank, so why does the address have to arrive at all drams simultaneously?

    Make sure each data byte is closely matched to it's strobe.

    Finally, make sure that the strobes are loosely aligned to the clock.

    If your customer is asking you to match Address to data, address (DRAM1) to address (DRAM 2) then I'm not sure they understand DDR.


    Originally posted in cdnusers.org by vealmic@uk.ibm.com
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.