Concept HDL Bus connection erorr

Hi there,
I do not think you need the merge / tie symbol in this instance. It is legal to draw the following busses in concept.

PPC_D<31..16>
Then somewhere else:
PPC_D<31..24>

Where <31..24> is a subset of <31..16>. You do not have to "declare" these with a merge symbol. However, the subset <31..24> is only usefull when connecting to a vectored pin. And I know you wouldn't want to draw a vectored pin on a component, becasue it makes debugging so difficult. :)

May I suggest :

1/ Where you want to use a subset <31..24> of the bus <31..16>, show the bus in it's entireity, <31..16> then show taps for each required bits, <31>, <30> ... <24>. That way anyone reading the schematic knows the correct size of the bus, and can see which bits you are using.

2/ Where the bus jumps through a vectored pin on a hierarchical block, again show the entire scope of the bus <31..16>. If you only need the subset in a different level of your hierarchicy, use the technique above. Bringing the entire bus through the hierarchy does not give dangling nets crossing the hierarchy when you move to layout.

Does that help?

If you were to rename the nets on your merge symbol as follows:

Left hand net: ALL_BUS<63..0>
Right hand top net: MSB_BUS<31..0>
Right hand bottom net: LSB_BUS<31..0>

It might better explain how the merge symbol should be used.
Note that on the left hand branch you now have 64 nets. And on the right hand branches, you have two lots of 32 nets.

In your example, you have 16 bits on the left hand branch, 8 nets on the top right and 16 on the bottom left.

16 != 8+16

Which is why you are getting an error.