Differential Pair Gather Points

Hi All, I'm hoping someone can help me to better control my differential pair routing. As some background, our boards typically contain 200+ differential pairs running at 2.5 Gbps. We typically fanout by hand all differential pairs from BGA land patterns or SMT pads and constain the router to route the pairs on mid layers only, using no vias. Crosstalk rules also apply here. Because of the high frequency content of these signals, we go through great pains post-route to ensure that the pairs are clean and coupled to the greatest extent possible. This involves ensuring that as the pairs enter the mid layer and begin their coupling that both legs exit the via pair and come directly together with the shortest length possible. The IDEAL routes are shown in the attached image. We're running v16.01 of the Allegro Autorouter and we always have great difficulty in controlling the endpoints of the differential pair. No matter how I constain it, a good number of pairs do not quickly come together but seem to do crazy things at the endpoints. See the NON-IDEAL routes in the attached image. I am wondering if anyone in the forum has experienced this and what cures they have if any. When dealing with boards of at least 200+ pairs, the misbehaviour of the router leads to tons of post-route cleanup time. Getting the router to produce clean routes all the time would greatly reduce our clean-up time not to mention decrease my headache size. Typical Pair Definition includes the following commands: define (pair (nets FPGA_LOCAL_19.44MHZ_P FPGA_LOCAL_19.44MHZ_N (gap 4.4))) define (class FPGA_LOCAL_19.44MHZ FPGA_LOCAL_19.44MHZ_P FPGA_LOCAL_19.44MHZ_N) circuit class FPGA_LOCAL_19.44MHZ (match_net_length on (tolerance 100)) rule class FPGA_LOCAL_19.44MHZ (width 3.6) rule class FPGA_LOCAL_19.44MHZ (max_total_vias 0) circuit class FPGA_LOCAL_19.44MHZ (use_layer Mid2 Mid3 Mid4 Mid5) rule class FPGA_LOCAL_19.44MHZ (max_uncoupled_length 0) rule class FPGA_LOCAL_19.44MHZ (min_line_spacing 4.4) rule class FPGA_LOCAL_19.44MHZ (edge_coupled_tolerance_minus 0) rule class FPGA_LOCAL_19.44MHZ (edge_coupled_tolerance_plus 0) rule class FPGA_LOCAL_19.44MHZ (neck_down_width 3.6) rule class FPGA_LOCAL_19.44MHZ (neck_down_gap 4.4) rule class FPGA_LOCAL_19.44MHZ (diffpair_line_width 3.6) rule class FPGA_LOCAL_19.44MHZ (edge_primary_gap 4.4) rule class FPGA_LOCAL_19.44MHZ (ignore_gather_length on) Thanks in advance for your thoughts, Chuck Remaley Design Engineer WMI, Inc.