CIS hidden symbol power pins causes strange Allegro behavior

No. That does not sound correct. Do you name your power and ground something other than VCC and GND? Packager will netlist these out as global connections to VCC and GND...

If possible, post your packager files (PSTXPRT.DAT, PSTCHIP.DAT, PSTXNET.DAT) so we can look.
Do both variations to examine what's going on -- or open up a SR with Cadence.

Too late. I fixed the problem. But still don't understand why it happened. I didn't do the schematic and I also didn't do most of the board layout.  I had to take over from an outside design house.  First, the power/gnd nets on the board are named +5V and GND_SIGNAL. Before I fixed it, the 2 one-pin nets were named VCC and GND (the same as the pin names which makes sense since these were hidden and I'm assuming that's what they should be connecting to). So I made the pins visible and took off the POWER use by editing the part in CIS. I made the pin use PASIVE. Then I ran a new netlist into the board but that didn't seem to work. So, in CIS, I removed the connections completely from those 2 pins and then ran a netlist into the board. So far so good. Those 2 pins became DUMMY nets. The I just added the connections back on the 2 pins in CIS and ran the new netlist into the board again. That did it. Now the 2 pins were linked to the correct nets (+5V and GND_SIGNAL) and the original nets were gone from the board. I've seen stuff like this before in other tools. Sometimes soemthing gets set internally and you have to 'force' it back. Thanks for asking redwire.  

redwire, by the way, i did look at all 3 packager files and searched thru them but didn't see anything unusual. So it leads me to believe the problem was in allegro.

Nope it's not allegro -- it's your schematic. I figured someone didn't know how the tool works and you've confirmed it.
VCC and GND pins get netted out to those *exact* net names. When someone uses "GND_SIGNAL" they are not using the symbol in a standard method leaving the net name the same as the symbol name. It should be named "GND" when being placed on the schematic.

And, why would you think that a net called "VCC" is the same as "+5V"? They are unique!

There is a simple 'override' feature in the packager when you place a property called "POWER_GROUP" onto the symbol. With it you can override the net name "VCC" with "+5V" with the addition of the property I just mentioned and its value "VCC=+5V"

All of this is explained in the docs.

Redline if you read my post you would have seen that I found out AND understood that the hidden pin names in the CIS symbol (VCC and GND) translated to nets being named VCC and GND in Allegro. With that, once again, i made the pins visible and connected them to the nets that were already in the schematic (+5V and GND_SIGNAL). So at this point, wouldn't you expect that after packaging, the 2 pins would then be connected to +5V and GND_SIGNAL in Allegro regardless of what the pin name was in CIS? (I even changed the pin type to Passive). But instead, it made all the GND_SIGNAL vias and C-lines into Dummy nets even though they were still connected to the pins which yielded alot of drc errors. Same goes for the other net. You did mention a property called POWER_GROUP. I looked at that and will try that Monday.