[help] about ConceptHDL signal name

This a function of the packager. It is unlikely that Cadence will change this behavior. There is a property on the schematic that can be seen in expanded mode (CDS_PHYS_NET_NAME) that will show the name that was passed to Allegro. You must have an environment variable set (SHOW_CDS_PROPS=TRUE) in order for this to work.

Hope this helps.

firstly, thank you Mr./Ms. Charlie davies.

you know that in the setting "net name length"("setup--tools--packager-xl-->layout), we can not set very short or very long,because our PCB software(not allegro) is limited the net name length 31.

we think that "UN......"(2character) is very clear, not need useing "UNNAMED......"(7character).
Concept SCALD's net name is used "UN......",but ConceptHDL's "UNNAMED......". why is it like this one?

in the packager-xl, how to set can we get "UN......"?

I don't know of anyway to eliminate the UNNAMED in the net name. Set the net name length to be equal to what your layout tool can support should result in unique signal names. I suspect that Cadence thought about that when they came up with the algorithm. If that doesn't work, I would suggest contacting Cadence and opening an SR.


Hope this helps.

Set the variable:

UNNAMED_NET_GEN to 'OFF'

Set this Variable in the project CPM area:

START_CONCEPTHDL
.
.
UNNAMED_NET_GEN to 'OFF'
.
.
END_CONCEPTHDL