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Forum - Thread List

Latest Posts

  • Discussion

    Design Parameters

    Category: PCB Design

    By Goblin60

    •

    updated over 15 years ago by KEN13

    4 replies • 14388 views
  • Discussion

    Cae Views HDL retreive bus from design

    Category: PCB Design

    By arge

    •

    started over 15 years ago

    0 replies • 12819 views
  • Discussion

    relative propagation delay problem

    Category: PCB Design

    By yosephcz

    •

    updated over 15 years ago by yosephcz

    2 replies • 15928 views
  • Discussion

    Orcad 16.2 - Create netlist error "CAP[0020]"

    Category: PCB Design

    By Strickland

    •

    updated over 15 years ago by Strickland

    2 replies • 2308 views
  • Discussion

    Customized title block-capture

    Category: PCB Design

    By MAAC

    •

    updated over 15 years ago by steve

    5 replies • 15471 views
  • Discussion

    PCBD editor 16.0 Documentation

    Category: PCB Design

    By Tiberinus

    •

    updated over 15 years ago by redwire

    1 replies • 13327 views
  • Discussion

    Component graphics with SKILL

    Category: PCB Design

    By arge

    •

    updated over 15 years ago by jone23

    2 replies • 13065 views
  • Discussion

    Tapering of nets using Allegro PCB Design CIS L-163

    Category: PCB Design

    By MAAC

    •

    updated over 15 years ago by redwire

    1 replies • 13345 views
  • Discussion

    Show Element to get netnames only?

    Category: PCB Design

    By Kory Johnson

    •

    updated over 15 years ago by Kory Johnson

    4 replies • 14495 views
  • Discussion

    Text block changes on export libs

    Category: PCB Design

    By Allan M

    •

    updated over 15 years ago by Allan M

    2 replies • 14165 views
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