• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      avant
      avant 55 Points
    • 1
      KS202606109251
      KS202606109251 55 Points
    • 3
      BC202603263145
      BC202603263145 26 Points
    • 4
      JV202605125312
      JV202605125312 20 Points
    • 4
      JR202606119023
      JR202606119023 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,598 Points
    • 2
      oldmouldy
      oldmouldy 10,805 Points
    • 3
      eDave
      eDave 7,391 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,231 Points
    • 5
      redwire
      redwire 4,458 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Identify unrouted nets

    Category: PCB Design

    By stellar

    •

    updated over 16 years ago by stellar

    8 replies • 21066 views
  • Discussion

    Same Net DRC for Stagged (Burried) vias

    Category: PCB Design

    By dhina

    •

    updated over 16 years ago by Helen

    1 replies • 14098 views
  • Discussion

    Backannotating mirror info from Allegro to Capture...

    Category: PCB Design

    By Dan08

    •

    updated over 16 years ago by Helen

    2 replies • 13977 views
  • Discussion

    Modelling the connectors for SI Analysis-163

    Category: PCB Design

    By MAAC

    •

    updated over 16 years ago by Khurana

    3 replies • 13983 views
  • Discussion

    Orcad PCB Designer - Place manual

    Category: PCB Design

    By Tory1

    •

    updated over 16 years ago by Tory1

    2 replies • 2141 views
  • Discussion

    DRC for ht mismatch in Allegro PCB-163

    Category: PCB Design

    By MAAC

    •

    updated over 16 years ago by steve

    7 replies • 16077 views
  • Discussion

    How to use skill file in allegro

    Category: PCB Design

    By kingshar

    •

    updated over 16 years ago by wolfwang

    9 replies • 20552 views
  • Discussion

    PCB Editor 16.2 generating faulty silkscreen.art files

    Category: PCB Design

    By kanonfodder

    •

    updated over 16 years ago by redwire

    3 replies • 14420 views
  • Discussion

    Problem with psp_eng.dll

    Category: PCB Design

    By elvik

    •

    updated over 16 years ago by elvik

    2 replies • 14192 views
  • Discussion

    Help with "FIXED" property

    Category: PCB Design

    By croc4

    •

    updated over 16 years ago by redwire

    6 replies • 13285 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information