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Forum - Thread List

Latest Posts

  • Discussion

    Defining Vias With Different Anti-Pads/Selected Layers In Positive Planes

    Category: PCB Design

    By aemeehan

    •

    updated over 7 years ago by aemeehan

    1 replies • 1897 views
  • Discussion

    Renaming caused problems with pin pair definitions

    Category: PCB Design

    By aemeehan

    •

    updated over 7 years ago by steve

    1 replies • 13980 views
  • Discussion

    Hide a schematic net name

    Category: PCB Design

    By Neil1234

    •

    updated over 7 years ago by Neil1234

    1 replies • 17334 views
  • Discussion

    Rat shown on via despite connection

    Category: PCB Design

    By Bijanbina

    •

    updated over 7 years ago by Bijanbina

    7 replies • 19562 views
  • Discussion

    OrCAD Capture Data Tip customization

    Category: PCB Design

    By chadga

    •

    updated over 7 years ago by steve

    2 replies • 16940 views
  • Discussion

    "there is no enough memory for this operation" when trying to plot in pcb editor

    Category: PCB Design

    By blackflowers

    •

    updated over 7 years ago by ajithomas

    4 replies • 4080 views
  • Discussion

    Capture crashes when running DRC

    Category: PCB Design

    By alfredojohnson

    •

    updated over 7 years ago by steve

    1 replies • 14457 views
  • Discussion

    Hierarchical ports moving around when adding and the synchronizing up...

    Category: PCB Design

    By UlfK

    •

    updated over 7 years ago by UlfK

    4 replies • 16294 views
  • Discussion

    Auto Rename Ref Des in 17.2 - space between characters?

    Category: PCB Design

    By aemeehan

    •

    updated over 7 years ago by aemeehan

    1 replies • 839 views
  • Discussion

    change Pin size of block in hierarchy design

    Category: PCB Design

    By Carson Yuan

    •

    started over 7 years ago

    0 replies • 14145 views
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