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  • Discussion

    [Done] why thermal reliefs in muti-layers board don't display ? Locked

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    Latest over 12 years ago
    by fxffxf
  • Discussion

    PCB Editor | Netlist/refdes List Not Updating Locked

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    0 replies
    Started over 12 years ago
    by jacob80
  • Discussion

    Problem placing multi-part schematic symbol in Allegro Design Entry Locked

    15880 views
    5 replies
    Latest over 12 years ago
    by chads108
  • Discussion

    Can we read an image file(*.bmp)

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    Latest over 12 years ago
    by baimage
  • Discussion

    Cannot add a custom Via: (Type Unknown) Locked

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    4 replies
    Latest over 12 years ago
    by Naroah
  • Discussion

    The Application has failed to start Locked

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    1 reply
    Latest over 12 years ago
    by oldmouldy
  • Discussion

    Learning Allegro Locked

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    Latest over 12 years ago
    by steve
  • Discussion

    Cadence Design Entry HDL connecting different widths buses Locked

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    Latest over 12 years ago
    by ksielewi
  • Discussion

    star point grounding Locked

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    Latest over 12 years ago
    by TooBorg
  • Discussion

    strange Design Compare behavior Locked

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    3 replies
    Latest over 12 years ago
    by davidsun
  • Discussion

    PCB Design with a Microcontroller (Orcad Layout/Capture/PSpice) Locked

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    0 replies
    Started over 12 years ago
    by Monte Porche
  • Discussion

    ERROR CAP0049 Locked

    14851 views
    1 reply
    Latest over 12 years ago
    by oldmouldy
  • Discussion

    Create Via library Locked

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    1 reply
    Latest over 12 years ago
    by VincentS
  • Discussion

    Hierarchical design Locked

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    1 reply
    Latest over 12 years ago
    by VincentS
  • Discussion

    Routing over voids Locked

    15389 views
    1 reply
    Latest over 12 years ago
    by oldmouldy
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