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    WARNING: You are making net VCC_USB_5V a DC net but it contains no power or ground pins Locked

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    0 replies
    Started over 12 years ago
    by KARPCB
  • Discussion

    Can I use forms on Design Entry HDL?

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    3 replies
    Latest over 12 years ago
    by aflex
  • Discussion

    How to create a netlst - Desing Entry HDL Locked

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    1 reply
    Latest over 12 years ago
    by PAVANRKS
  • Discussion

    Checklist Autofill

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    4 replies
    Latest over 12 years ago
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  • Discussion

    16.5 Autorouting Error: SPECCTRA quit unexpectedly with an exit code of 19 Locked

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    2 replies
    Latest over 12 years ago
    by dforsyth1
  • Discussion

    Problems with Vias Locked

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    2 replies
    Latest over 12 years ago
    by NicoDD
  • Discussion

    HOW to enable the Find Window? Locked

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    2 replies
    Latest over 12 years ago
    by KARPCB
  • Discussion

    copy between designs? Locked

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    3 replies
    Latest over 12 years ago
    by redwire
  • Discussion

    How to check and verify negative artwork? Locked

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    0 replies
    Started over 12 years ago
    by binpersonal
  • Discussion

    Why can't you slide components? Locked

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    4 replies
    Latest over 12 years ago
    by aricbeaver
  • Discussion

    How to vertical how horizen mirror a pad in Allegro package symbol? How to clean design cache? Locked

    20922 views
    8 replies
    Latest over 12 years ago
    by Leeya
  • Discussion

    create a association list using a variable for the value??

    14203 views
    2 replies
    Latest over 12 years ago
    by jwhend
  • Discussion

    Error while loading the .il file

    18670 views
    6 replies
    Latest over 12 years ago
    by Andrew Beckett
  • Discussion

    Table of Contents generator for Capture Locked

    15538 views
    1 reply
    Latest over 12 years ago
    by steve
  • Discussion

    Reuse Module with different stackup Locked

    17277 views
    6 replies
    Latest over 12 years ago
    by steve
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