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  • Discussion

    How to insert True Type text into PCB design (silk screen)? Locked

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    1 reply
    Latest over 14 years ago
    by oldmouldy
  • Discussion

    Orcad 16.4 -> Save as 16.2 Locked

    1095 views
    1 reply
    Latest over 14 years ago
    by steve
  • Discussion

    teardrops

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    2 replies
    Latest over 14 years ago
    by fxffxf
  • Discussion

    How do I attach a SV interface to verilog modules? Locked

    12559 views
    0 replies
    Started over 14 years ago
    by JackieP
  • Discussion

    Add signal name to PWR and GND symbols --- Design Entry HDL 16.5 Locked

    2329 views
    3 replies
    Latest over 14 years ago
    by Jerry GenPart
  • Discussion

    how to z copy routes in allegro Locked

    17505 views
    4 replies
    Latest over 14 years ago
    by mcatramb91
  • Discussion

    Getting FQN of the current board file

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    3 replies
    Latest over 14 years ago
    by PatrickEscher
  • Discussion

    Getting path for loaded skill file

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    6 replies
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    by Ejlersen
  • Discussion

    Routing net length in Cadence 16.2 Locked

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    2 replies
    Latest over 14 years ago
    by redwire
  • Discussion

    How do I cut a rectangular slot in my PCB (rounded corners ok) Locked

    14942 views
    2 replies
    Latest over 14 years ago
    by KEN13
  • Discussion

    Mechanical pad Locked

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    4 replies
    Latest over 14 years ago
    by RiskCord
  • Discussion

    valor check result error help Locked

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    2 replies
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    by purikku22
  • Discussion

    PSpice question Locked

    13933 views
    4 replies
    Latest over 14 years ago
    by Radio Stanice
  • Discussion

    errport or poport messages reading

    12679 views
    0 replies
    Started over 14 years ago
    by Kadar
  • Discussion

    Reuse code, libraries, inclusion mechanism.

    4740 views
    0 replies
    Started over 14 years ago
    by Silver John
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