Exploring 3D Via Modeling and Simulation Using Sigrity X and Clarity 3D Solver

As data rates continue to increase, vias become a critical part of the signal path and can significantly influence overall channel performance. Accurate 3D via modeling helps engineers better understand the impact of via discontinuities, parasitic effects, return paths, and routing constraints on signal integrity.

Cadence Sigrity Topology Workbench includes the Aurora Via Wizard, which enables users to create detailed 3D via structures, visualize the geometry, extract EM-accurate models using the Clarity 3D field solver, and use those models directly in system-level simulations.

Key capabilities include:

• Defining custom stackups and cross-sections
• Creating single-ended or differential via structures
• Configuring padstacks, return paths, and keepout regions
• Visualizing 3D via geometry
• Extracting S-Parameter models using Clarity 3D
• Integrating the extracted via models into Topology Workbench simulations
• Analyzing waveform behavior and channel performance

The workflow begins by adding a Via block in Topology Workbench and launching the Aurora Via Wizard from the Via Properties panel.

A typical flow includes:

1. Define the Cross-Section.

Create the stackup and plane definitions required for accurate via modeling. Proper reference planes are essential for successful port definition and EM extraction.

2. Configure Padstacks and Via Structures.

Select padstacks, create single-ended or differential via structures, and define return vias, spacing, angles, and keepout regions.

3. Visualize the 3D Geometry.

Review the generated via structure in a 3D environment to verify the physical implementation before extraction.

4. Extract the Via Model.

Generate an EM-accurate S-Parameter model using the Clarity 3D field solver and automatically assign the model to the Via block in Topology Workbench.

5. Simulate and Analyze.

Connect the extracted via model to transmitter and receiver blocks, perform transient simulations, and evaluate waveform quality and signal integrity metrics.

By incorporating realistic via behavior into early design analysis, engineers can improve correlation between simulation and hardware performance while gaining deeper insight into channel discontinuities and interconnect effects.

To learn more about 3D via modeling and simulation workflows, explore the Aurora Via Wizard capabilities available in Sigrity Topology Workbench.

Click here for more details on 3D via modeling and simulation using Sigrity.

Have you used 3D via models in your high-speed designs? What challenges or best practices have you observed when modeling vias for SI analysis? Share your thoughts in the comments below.

Thanks & Regards,

Shiva Shankar M