Importance of Models in Signal Integrity Simulations

Electronic Engineers designing high-speed systems need to ensure first-time-right designs to avoid huge costs of re-spinning and time-to-market overruns. Design engineers depend on system analysis and prototyping tools to mitigate malfunctioning and rework risks. These analysis and prototyping tools depend on the accuracy of the models.

To ensure industry-standard performance, these models must ensure behavior close to the real world, which is achieved through model validation. The various system-level models include IBIS, IBIS AMI, S-Parameters, Broadband SPICE models, RLC Model, Chip IO Model, and so on.

What is a model?

A model is an electrical representation of a physical device.

For example, a flip-chip package can be represented as a combination of several sections of RLGC components.

Importance of modeling

Transmission lines, PCBs, packages (flip-chip/wire bonds), connectors, vias, return paths, and so on can be modeled in a very detailed way using the Extraction and Analysis software. However, if the simulation setup is not done correctly, the model generated would not be accurate.

Engineers must understand the origin of model data and be familiar with modeling types and limitations. Also, they need to know how the tool uses the model data.

Consider a DDR System-Level Topology in Sigrity Topology Explorer (TopXp) with its numerous models.

IBIS Models: Cadence Sigrity T2B (Transistor-to-Behavior modeling)

IBIS models are behavioral buffer models based on I-V curves and Ramp data or V-T curves. There is no design detail in these buffer models. The output impedance of the buffer is characterized with I-V curves, and their switching characteristics are characterized with the Ramp or V-T curves. Hence, these models are much faster as compared to the traditional Spice-level netlists.

You can get more information about the IBIS Models by clicking here.

IBIS AMI: Cadence AMI Builder (Algorithmic Modeling Interface)

IBIS-AMI models contain complex signal-processing algorithms. The input to these models is an impulse response of the channel, and the AMI models apply their signal-processing algorithms to them to obtain results. The wizard-based approach walks the user through a series of questions and builds a block-based topology of equalization elements. The block-based modeling environment allows monitoring of the signal through each phase of the equalization.

You can get more information about the IBIS AMI Models by clicking here.


Chip IO / DIE Models: Voltus and Xcite PI

The Chip IO / DIE Model contains the switching activity of the chip. XcitePI/Voltus is a full-chip power integrity solution targeting on chip/system co-design applications. It supports early chip power planning, IO and core model extraction, and simulation in both the time and frequency domains.

You can get more information about the Voltus generated Chip IO Model by clicking here.

You can get more information about the XcitePI generated Chip IO Model by clicking here.

PCB Model – S-Parameters: Power SI

S-Parameters refer to the Scattering Parameters, and it has all the information about the electrical behavior of the linear circuit elements, basically the PCB/Packages, etc.

PowerSI is advanced signal integrity, power integrity, and design-stage EMI solution. It supports the s-parameter model extraction and provides a robust frequency-domain simulation for the entire IC package and PCB designs.

You can get more information about the extraction of s-parameters from PowerSI by clicking here.

Package RLC Model: XtractIM

The Sigrity XtractIM technology gives you electrical models of IC packages in IBIS or SPICE circuit netlist format. These concise parasitic models can be per pin/net RLC list, coupled matrices, or Pi/T SPICE subcircuits.

You can get more information about the extraction of the RLC Model from XtractIM by clicking here.