Sigrity Topology Explorer Parallel Bus Analysis Workflow - Accurately assess high-speed, chip-to-chip system designs

Today’s high-speed bus interfaces, such as DDRx and LPDDRx memory designs, are characterized by tight timing margins and analysis requirements that cross chip, package, and board structures. With the Sigrity Topology Explorer 17.4 Parallel Bus Analysis (PBA) workflow approach, you get support for concurrent simulation that accounts for the effects of dielectric and conductor losses, reflections, inter-symbol interference (ISI), crosstalk, and simultaneous switching noise (SSN). This is essential for emulating real hardware behavior.

It is integrated with the Sigrity-patented board and package modeling tools, including PowerSI, for extraction of accurate hardware interconnect models and real power distribution networks. The tool supports IBIS behavioral I/O models with non-ideal power conditions. Interconnects like connectors and cables can be included with S-parameter data or SPICE-compatible circuit models. Synchronous design performance metrics including eye diagrams with detailed timing measurements are available with reference to JEDEC standards.

To get started with exploring various tool capabilities for solving design challenges refer the Rapid Adoption Kit from here