In-Design Impedance Analysis

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” High-speed traces on a board are laid out most carefully, but the remaining traces are often sent for manufacturing without any inspection after routing.

In-Design Impedance Workflow powered by the Sigrity hybrid solver allows the entire post-layout board to be analyzed quickly and easily to avoid costly layout mistakes that can cause a board re-spin and delay a project. Anyone can run this analysis through the Workflow Manager and view impedance results directly on the canvas. The full cross-sectional geometry is used to compute accurate impedance results presented in a table with characteristic impedance, delay, and RLC values for each net and segment within a net.

For most designs, the analysis takes seconds to run on all signal nets. The results can easily be exported as a CSV file, making it possible to quickly create post-layout reports and share your design details outside of Allegro PCB Editor.

Watch the video here demonstrating the steps to determine impedance mismatch issues in a PCB.

Team SimTech

Cadence Design Systems