When designing a PCB, it is important to carry out IR drop analysis to minimize IR drop and achieve PI in the PCB. It is suggested that you place the sources and sinks with the shortest possible interconnections in PDNs. You might be wondering the reasoning behind this PCB design rule - it lies in the IR drop (V=IR). The shorter the connecting wires in PDNs, the higher the Power Integrity (PI) of the analog layout. As a PCB team member, you should be discussing PI in every meeting you have, since the PI in PCB layouts is very important. 

The IR drop in PDNs is the main threat for achieving the PI. For a given PCB with fixed power rating and finite trace resistance, excessive current flow through PDNs generates IR drop and a rise in temperature, which also worsens the situation. Similarly, the localized hotspots in the PCB layout due to the Swiss-Cheese effect are not favorable for your PDN design. 

Factors Controlling IR Drop in PCB Planes

There are many interdependent factors that can impact IR drop, including the following: 

• Single-sided or double-sided PCBs
• Signal flow path
• Trace geometry
• Thermal effect
• Impedance matching between the different traces of different layers
• Count and size of vias

You can minimize these IR drops using Sigrity PI Tool – PowerDC. You can work on trace geometry, component placement, and re-routing in the PCB layout by understanding the IR drop simulation results. 

Click here to learn more about techniques to minimize IR drop.