Crosstalk Analysis and Simulation in High-Speed PCB design

Today’s modern digital systems are all high-speed systems, and high-speed PCB design is no longer a specialized discipline. Low-speed protocols like SPI and I2C are not going away anytime soon, but they can’t handle the high data demands of modern computing and embedded systems. With high-speed signals comes signal and power integrity problems, as well as EMI/EMC challenges and the need for simulations to validate designs. 

Crosstalk is one signal integrity problem that can be masked by other signal and power integrity problems that create noise in high speed channels. High-speed PCB design must confront crosstalk to ensure signal integrity. 

Fill in Gaps Using Crosstalk Analysis and Simulation in High-Speed PCB Design 

Crosstalk analysis and simulation in high-speed PCB design should focus on narrowing down to the major offending pairs of nets that should be modified to prevent crosstalk. These nets can often be found in a few specific places in a PCB layout: 

• High-speed nets routed in parallel on adjacent layers 
• Single-ended nets being routed very close to differential nets 
• High-speed nets that are very densely routed 

Click here to learn more about crosstalk analysis and simulation in high-speed PCB design. 

You can also check the Application Note here to learn about how to perform crosstalk analysis using Cadence Sigrity and PCB design tools. 

Team SimTech

Cadence Design Systems