Importance of Package parasitics of a buffer model in TopXp PBA and SLA analyses

In newer high-speed digital applications, where multiple data lines can run up to 10s of Gbps, parasitics capacitance and inductance of a buffer model can produce impedance mismatch along the signal path. Any mismatch caused by parasitics will produce reflections somewhere down the line, ultimately increasing timing jitter and bit-error rates. Therefore, Package parasitics can never be ignored in any high-speed systems.

Package Parasitics:

The electrical elements (that is, resistance, inductance, and capacitance of a circuit), which are possessed by the package model of a device but are not desirable for it to have for its intended purpose, are known as Package parasitics. These parasitics elements of a package are unavoidable.

It is often necessary to include the effects of Package parasitics values of a buffer model when performing system-level simulations in Topology Explorer. The Package parasitics of a device model are obtained from its IBIS model. Therefore, these Package parasitics of a buffer model are very important in high-speed systems.

Just like OnDie parasitics, you can also observe the impact of Package parasitics in Sigrity Topology Explorer PBA and SLA analyses.

Parallel Bus Analysis:

When performing channel simulations in Topology Workbench PBA, the following results can be obtained with Package parasitics enabled for both Controller and Memory blocks.

From the above figures, it can be seen that Package parasitics have a significant effect on channel simulations of TopXp Parallel Bus Analysis.

Serial Link Analysis:

When performing channel simulations in Topology Workbench SLA, with Package Parasitics enabled, the following results can be obtained.

It is evident from the above results that when Package parasitics enabled, there is significant effect on Serial Link Analysis. It is also observed that when Package parasitics are enabled, the Eye Height and Eye Width are reduced when compared to SLA topology with Package parasitics disabled.

Click here to learn more about Package parasitics of a buffer model in Sigrity Topology Workbench.

Team SimTech

Cadence Design Systems