How to constrain actual via current as per IPC-2221A specification in PowerDC

Understanding the current distribution for a via array is a critical step towards reducing the DC current value locally, which is a common task for power-integrity engineers, because they are required to provide means to reduce the DC current for some vias.

You can obtain the actual via current and max via current for each via in a design layout by using Sigrity PowerDC. Once simulations are completed, you can compare both currents. This helps analyze the current distribution in a via array.

In Sigrity PowerDC, electrical constraints can set up the max current for vias or padstacks.

1. In the PowerDC, select Set up E-Constraints under the Constraints Setup
2. In the Via Current/Current Density tab, select Setup by PadStack.
3. Use the pulldown under PadStack Name to select a padstack.
4. Assign the Maximum Current(A) constraint as per the IPC-2221A specification.

Run simulations and your constraint and actual current results for vias will be displayed in the Specific Via Current tab of the results table.

Team Sim Tech,

Cadence Design Systems.