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why does most of current flow to the center via under a mosfet

GDee1

the DPAK MOSFET has thermal vias under its main pad, and these thermal vias also are used to connect the copper plane at different layer. The PowerDC analysis shows that most current flows to the center of the vias ( I will say 60% of the total current). This sim result will make impossible to pass sim because the program thinks the current from MOSFET flows from its center to the lower copper plane.

I wish it is caused by my setup. could you please advise?

Thank you.

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