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Troubleshooting Signal Integrity Issues in Custom PCB Design - Emmanuel Katto

emmanuelkatto

Hello Cadence Community,

My name is Emmanuel Katto. I’m currently working on a custom PCB design using Cadence tools and have run into some signal integrity issues that I’m hoping to resolve. Here are some specifics:

  1. I am experiencing unexpected reflections on my high-speed signal traces. Are there recommended design practices or tools within Cadence to analyze and mitigate these reflections?
  2. What settings or simulations should I consider in Cadence's tools (like Sigrity) to assess the impact of my PCB layout on signal integrity?
  3. Are there common pitfalls to avoid during the layout phase that could lead to signal integrity problems in high-speed designs?

I appreciate any advice or shared experiences that could help me troubleshoot these issues.

Thanks in advance!

Emmanuel Katto

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  • Hi Emmanuel,

    1.General design best practices for reflection are avoid impedance mismatching and big discontinuities like a via stub.

    2. Cadence Sigrity Reflection workflow allow you to quickly identify the relative impact of layout features and routing on signal reflections

    You can get it from COS (Cadence Online Support) portal. For example, click the below COS link for Aurora Topology Extraction Workflow RAK:

    Sigrity Aurora: Reflection Workflow: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009m6PQEAY 

    You can also extract S-Parameter and take a look into the TDR response to identify discontinuities.

    3. Impedance mismatching, via stub, traces running too close to each other, lack of return path are common pitfalls to avoid/be aware during the routing.

    Thanks,

    Javier

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  • Hi Emmanuel,

    1.General design best practices for reflection are avoid impedance mismatching and big discontinuities like a via stub.

    2. Cadence Sigrity Reflection workflow allow you to quickly identify the relative impact of layout features and routing on signal reflections

    You can get it from COS (Cadence Online Support) portal. For example, click the below COS link for Aurora Topology Extraction Workflow RAK:

    Sigrity Aurora: Reflection Workflow: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009m6PQEAY 

    You can also extract S-Parameter and take a look into the TDR response to identify discontinuities.

    3. Impedance mismatching, via stub, traces running too close to each other, lack of return path are common pitfalls to avoid/be aware during the routing.

    Thanks,

    Javier

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