Mitigate Signal Reflection Issues in High-Speed Designs

High-speed designs are prone to problems like reflection and ringing, which can be detrimental to signal integrity. To avoid these issues, it's crucial to simulate and analyze your designs proactively.

Simplify Signal Reflection Analysis with Integrated Workflows

Our intuitive analysis workflows allow you to simulate, analyze, and resolve signal reflection problems directly on your canvas. Simply select the nets of interest and initiate the analysis.

Easily Identify and Fix Signal Reflection Issues

In this example, we're analyzing a DDR data net. The signals are color-coded to indicate the level of reflection, and you can view detailed information in a table. The red-coded DQ net shows a negative ring back margin, indicating excessive ringing due to impedance mismatch caused by a split plane.

Design Tip: Optimize Your Design

To fix this issue, move the reference plane to minimize impedance mismatch and re-run the analysis.

The Reflection Table provides a comprehensive view of voltage and timing measurements, including ring back margin, propagation delay, and more.

Common Causes of Signal Reflection

Impedance mismatches, return path gaps, and signal discontinuities can all contribute to signal reflection. With our integrated analysis, you can quickly identify and fix these issues.

Get Started with Reflection Analysis

Click this Ask Portal link to get a material reference about how to run Reflection Analysis in Sigrity Aurora Workflow.

Best regards,

Javier Alvarado