PDN Impedance Simulation

Question

Hi everyone, 
 I have a trouble with my PCB high-speed designs. 
 I have 2 designs called Design A and Design B with details information for my POWER like that: 
 Design A have 20 VCC De-CAPs with total capacitance value is 178.6uF 
 Design B have 33 VCC De-CAPs with total capacitance value is 430.4uF 
 In theory, the impedance in Design B is better than (Lower Impedance) the impedance in Design A 
 In fact, when I run PI simulation about the PDN imdedance for this POWER. I see that the impedance at AC range ( > 2MHz) is OK but the DC range ( 0 to 2MHz) is NOT OK. 
 The DC range, the impedance in Design B is higher than the impedance in Design A. It's NOT good! I expected the opposite. I expect these 2 DC results to be at least equal about the Impedance. 
 Can anyone explain this simulation result to me? 
 Thank you!

Sumith · Accepted Answer

Hi HirosakiOnda, have you considered enhancing the AC-DC fitting? Alternatively, you might find it effective to replace the capacitor with ports at lower frequencies. Another option could be to enable IPC mode for the analysis.

OscPn · Answer

With more capacitors in Design B, you may have a longer power path and more vias, which can contribute to an increase in total DC resistance. This additional resistance can dominate the impedance at DC range, making it higher than the impedance in Design A.

HirosakiOnda · Answer

Hi Sumith, 
 I solved this problem, the cause here is that my files conflicted when converting to .spd I deleted all the data and started over and it didn't happen again. 
 Thanks so much for the information!

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PDN Impedance Simulation

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