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How to assign a group of BGA pin in OptimizePI

HASAN2024

Hi there, 

I got stuck, with a simulation in OptimisePI, 

My board is bit different; it has 4000 BGA pins in bottom  and over 500 decaps.

Now , let me give you some examples then it will be easy for you to understand what I want to do.

 

Power Integrity analysis

Impedance checking

IC Device Power Pin Inductance Analysis

 

Setup

Frequency 1MHz (default)

VRM not defined

All VDDC caps are shorted

 

Need to simulate :

BGA pin inductance( Inductance observed at VDDC BGA pins ,BGA pins are defined as IC device. 

Let me  know how I can make net for this type of BGA pin row, 

 https://drive.google.com/file/d/1PtezuAY4AOoQTkx9QOZCZwMRaqkof9gE/view?usp=drive_link

BGA pin inductance a polygon is placed over the BGA row and the capacitor package keep-out/ mask is present there.

And most importantly, I don’t know how the engineer has ordered the BGA row with caps, he mentioned in his simulation result like, Row AG-BG/ Row BJ-CJ/ Row CL-DJ, where the caps are considering vertical and horizontally placed in layout. Any axis rotation?

 

  • ShivaShankarM
    0

    Hi Hasan, Nice to meet you!!

    I assume that you're trying to perform Power Pin Inductance simulation for your IC device using Sigrity OptimizePI. 

    Typically, net assignments for BGA Pins are performed during the design stage before importing to Sigrity. I was wondering if you designed the board in the Allegro environment? Before proceeding, did you verify the cross-section, component models and net assignments for BGA pins to ensure they are accurate before importing into OptimizePI?

    Thanks,

    Shiva Shankar M

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