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  3. SI Engineers, This One's for You! - Live Experts Session...

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SI Engineers, This One's for You! - Live Experts Session on Aug 19th 2026

Renu Vibha
Renu Vibha 21 days ago

Curious about S-Parameters, Insertion Loss, or Return Loss?

Bring your questions and join our upcoming Cadence Sigrity SI/PI Live Experts Session.

Learn proven analysis techniques, hear practical use cases, and interact directly with Cadence specialists.

Topic - Pre-layout Simulations covering Aurora Workflows, Topology Workbench (Pre-layout), Power SI ERC

Participate here  on August 19th at 7:30-8:30PM IST.

Bring your questions. Leave with answers

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  • AK20250609765
    AK20250609765 4 days ago in reply to EDAHut +1
    Thank you for the question. To maintain the validity of pre-layout signal integrity (SI) results when the PCB stackup changes during the design cycle, follow these steps: Correctly Model Devices: Ensure…
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  • CF202606104231
    0 CF202606104231 4 days ago

    What new challenged does AI servers and high performance computing systems present for SI Engineers. Can you throw some light

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  • CF202606104231
    0 CF202606104231 4 days ago

    What new challenged does AI servers and high performance computing systems present for SI Engineers. Can you throw some light

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  • AK20250609765
    0 AK20250609765 4 days ago in reply to CF202606104231

    Thank you for the question.

    AI servers and high-performance computing (HPC) systems introduce several unique challenges for signal integrity (SI) engineers:

    1. Heterogeneous Architectures: The integration of various processing units, such as CPUs, GPUs, and AI processors, requires careful management of signal integrity across different components, which can complicate design and validation processes.
    2. High-Speed Signaling: The demand for high-speed data transfer increases the risk of signal integrity issues, including crosstalk, attenuation, and reflections. Engineers must implement advanced techniques to mitigate these effects.
    3. Memory Bandwidth Limitations: The "memory wall" phenomenon, where memory bandwidth does not scale with the number of cores, poses challenges in ensuring that data can be efficiently accessed and processed without bottlenecks.
    4. Thermal Management: Increased power consumption from high-performance components generates heat, which can affect signal integrity. Engineers must design effective cooling solutions to maintain optimal operating conditions.
    5. Electromagnetic Interference (EMI): The complexity of modern AI workloads can lead to increased EMI, necessitating careful design to minimize interference and ensure compliance with regulatory standards.
    6. Complex Routing Constraints: The intricate layouts required for high-speed signals on PCBs can lead to routing challenges, requiring innovative design strategies to maintain signal integrity.
    7. Modular Designs: The shift towards disaggregated architectures and modular designs, facilitated by standards like UCIe, requires SI engineers to adapt to new connectivity standards and ensure compatibility across diverse components.

    Addressing these challenges is crucial for the successful deployment of AI servers and HPC systems, ensuring reliable performance and efficiency in demanding environments.

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